New fuse structure

ABSTRACT

An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

This application claims the benefit of U.S. Provisional Application No.60/583,637, filed on Jun. 29, 2004, entitled “E-Fuse Structure Design inElectrical Programmable Redundancy for Embedded Memory Circuit,” whichapplication is hereby incorporated herein by reference.

TECHNICAL FIELD

This invention relates generally to an electrical fuse and moreparticularly to an electrical fuse having a vertical structure.

BACKGROUND

In the semiconductor industry, fuse elements are widely used features inintegrated circuits for a variety of purposes, such as improvingmanufacturing yield or customizing a generic integrated circuit. Forexample, by replacing defective circuits on a chip with redundantcircuits on the same chip, manufacturing yields can be significantlyincreased. Replacing defective circuits is especially useful forimproving manufacturing yield of the memory chips since memory chipsconsist of a lot of identical memory cells and cell groups. Byselectively blowing fuses within an integrated circuit that has multiplepotential uses, a generic integrated circuit design may be economicallymanufactured and adapted to a variety of custom uses.

There are two different ways to disconnect fuses: in one way, thedisconnection is carried out by the action of a laser beam, and the fuseis referred to as a laser fuse. In another way, the disconnection iscarried out by electrical destruction resulting from the production ofheat. The fuse is referred as an electrical fuse, or E-fuse.

Laser programmable redundancy has been widely used in large-scale memorydevices. However, the laser repair rate in various structures such as inlower level metal layers is low and the process is complex. FIG. 1illustrates a laser fuse formed close to the surface of a chip. Device 6is a laser fuse. Oxide 5 covers the fuse 6. If the fuse 6 is to beburned out from top of the oxide 5 by laser, the thickness T of theoxide 5 has to be within a certain range, for example, between about 0.1kÅ to about 4.0 kÅ. Therefore, an extra mask is needed to form theopening 4, and the process has to be precisely controlled. If a laserfuse 10 is in a lower level layer deep in a chip, as shown in FIG. 2,the opening 8 will be deeper, while the thickness T of the oxide stillhas to be controlled precisely, which increases the complexitysignificantly and decreases the repairable rate.

In addition, as technology is scaling down to 0.13 μm or below, copperis implemented as interconnects or power lines. Copper is a materialwith high current density tolerance and is not easily burned out byusing a laser gun. Furthermore, the combination of copper plus low-kmaterial 12 (used as inter-layer dielectrics) is becoming a trend toimprove RC delay. However, low-k material 12 cracks easily when etchingthe opening 8 in FIG. 2. This decreases the device reliability andincreases the production cost.

Electrical fuses were developed to improve repairable rates. FIG. 3illustrates a conventional electrical fuse 13. A polysilicon strip 15 isformed and patterned. The regions 14 and 16 of the polysilicon strip 15are doped with p+ and n+ dopant. The central region 18 is left un-doped.A silicide 20 is formed over the polysilicon strip 15. Before the fuse13 is burned out, its resistance is mainly determined by the resistanceof the silicide 20 so that the resistance is low. When a predeterminedprogramming potential is applied across the silicide layer 20 from nodes22 and 24, the silicide layer 20 agglomerates to form an electricaldiscontinuity. Therefore the resistance of the fuse 13 is mainlydetermined by the underlying polysilicon strip 15 so that the resistanceis significantly increased. The central un-doped region 18 makes thefuse resistance higher. The electrical fuse shown in FIG. 3 typicallyhas a higher repairable rate than a laser fuse. However, the repairablerate is still not satisfactory. Additionally, the fuse of FIG. 3 isformed laterally and occupies more layout space.

There are several disadvantages faced by conventional methods of makingfuses. Firstly, the repairable rate is typically low. Secondly, theadditional masking layer needed for laser repair incurs higher costs.The process is also more complex with higher uncertainty. Thirdly, thestructure design is not flexible. Fuses typically have to be designed inhigher layers, as it is harder to form deep laser trenches through tolower layers. Therefore, new methods of designing e-fuses are needed.

SUMMARY OF THE INVENTION

The preferred embodiment of the present invention presents a method offorming an electrical fuse having a vertical structure.

In accordance with one aspect of the present invention, a first-layerconductive line is formed on a base material. A via is formed over thefirst-layer conductive line. The via preferably comprises a barrierlayer and a conductive material. A second-layer conductive line isformed over the via. A first external pad is formed coupling thefirst-layer conductive line. A second external pad is formed couplingthe second-layer conductive line. The via, first conductive line andsecond conductive line are adapted to be an electrical fuse.

In accordance with another aspect of the present invention, copper isused in the via, the first-layer conductive line, and the secondconductive line. Single or dual damascene processes are used to form thevia, the first-layer copper line and the second-layer copper line.

The vertical structure of the preferred embodiment is suitable to beformed in any layer and saves layout space. The embodiments of thepresent invention have several advantageous features. Firstly, higherrepairable rates can be achieved since the burn out process is easier tocontrol and more reliable. Secondly, fewer masking layers are required,therefore reducing costs. Thirdly, the fuse may reside in any region ofthe inter layer vias for cell size reduction. This provides a flexiblestructure for circuit design.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a laser fuse formed close to the surface of a chip;

FIG. 2 illustrates a laser fuse formed deep in a chip;

FIG. 3 illustrates a conventional electrical fuse;

FIGS. 4 through 7 are cross-sectional views of intermediate stages inthe making of a preferred embodiment of the present invention;

FIGS. 8 through 12 are cross-sectional views of intermediate stages inthe making of a preferred embodiment of the present invention using adamascene process;

FIG. 13 illustrates three vias stacked;

FIGS. 14 a and 14 b illustrates borderless and non-borderless vias;

FIGS. 15 a and 15 b illustrate an application of the preferredembodiment of the present invention;

FIGS. 16 through 18 illustrate another preferred embodiment of thepresent invention; and

FIGS. 19 a and 19 b illustrate burned out fuses.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent invention provides many applicable inventive concepts that canbe embodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the invention, and do not limit the scope of the invention.

The preferred embodiments of the present invention present a novelmethod of forming e-fuses. A via connecting a lower-layer conductiveline and an upper-layer conductive line is adapted to be an e-fuse. Thee-fuse can be burned out by applying a voltage on external pads that arecoupled to the lower-layer conductive line and the upper-layerconductive line. Throughout the description, conductive lines are alsoreferred to as conductive layers.

FIGS. 4 through 7 are cross-sectional views of intermediate stages inthe making of a preferred embodiment of the present invention. It is tobe noted that the cross-sectional views are taken in a planeperpendicular to the length direction of the conductive lines formed.Therefore, conductive lines appear to be rectangles. FIG. 4 illustratesthe formation of a lower-layer conductive line 44 on a base material 40.The lower-layer conductive line 44 is preferably a metal comprisingtungsten, aluminum, copper, silver, gold, alloy thereof, compoundsthereof, and combinations thereof. It can also be formed of othermaterials such as doped polysilicon. Base material 40 is typically aninter-layer dielectric (ILD) also sometimes known as a pre-metaldielectric (PMD) or an inter-metal dielectric (IMD) layer. It can alsobe formed of other non-conductive materials such as a contact etchingstop layer (CESL).

An ILD layer 42 is formed beside the low-layer conductive line 44. TheILD layer 42 is preferably silicon dioxide deposited using, e.g.,tetraethyl orthosilicate (TEOS), chemical vapor deposition (CVD), plasmaenhanced CVD (PECVD), low pressure CVD (LPCVD), or other well-knowndeposition techniques. ILD 42 can also be other materials such asphospho-silicate glass (PSG) or other known materials. Typically, ILDlayer 42 has a low dielectric constant (K value) so that the parasiticcapacitance between conductive lines is reduced.

FIG. 4 also shows an etching stop layer (ESL) 46 formed on thelower-layer conductive line 44. The ESL 46 is preferably a dielectricformed of an oxide or other materials such as silicon nitride. An ILD 48is formed on the ESL 46. The ILD 48 provides insulation between thelower-layer metal line 44 and overlying conductive lines that will beformed subsequently.

FIG. 5 illustrates a via opening 50 formed in the ILD 48 and ESL 46. Aphoto resist material (not shown) is formed and patterned over the ILD48. The via opening 50 is formed in the ILD 48 and stops at the ESL 46.The ELS 46 protects the underlying lower-layer conductive line 44 whenthe ILD 48 is etched. Next, the exposed portion of ESL 46 is etched.Because the ESL 46 is quite thin relative to the ILD 48, process controland end-point detection are much more closely controlled, thus limitingthe likelihood of over-etching through the underlying lower-layerconductive line 44.

FIG. 6 illustrates the device after via 54 is formed in the contactopenings. In the preferred embodiment, via 54 is formed of tungsten,aluminum, copper, silver, gold, or combinations and other well-knownalternatives. In other embodiments, it can be formed of dopedpolysilicon. Preferably, via 54 has a composite structure, including abarrier layer 52 formed of a material comprising titanium, titaniumnitride, tantalum, tantalum nitride, silicon carbide, siliconoxycarbide, combinations thereof and other layers. The barrier layer 52prevents the via material diffusing into the ILD 48, which would causedevice failure. The thickness of the barrier layer 52 is preferablybetween about 10 Å to about 1000 Å, more preferably about 300 Å. Via 52and lower-layer conductive line 44 share an interface 49.

An upper-layer conductive line 58 and an ILD 56 are then formed usingthe methods mentioned in previous paragraphs, as illustrated in FIG. 7.The upper-layer conductive line 58 is in a layer higher than the layerin which the lower-layer conductive line 44 is formed. Interface 55exists between via 54 and the upper-layer conductive line 58. Bothlower-layer conductive line 44 and upper-layer conductive line 58 arecoupled to external pads 59 and 61, respectively. External pads 59 and61 are formed at the surface of the chip. The structure formed inprevious steps results in an electrical fuse that is defined in a regioncomprising via 54, interfaces 49 and 55 and surrounding regions. Byapplying a voltage to external pads 59 and 61, a current flows throughthe fuse and a discontinuity is formed in the fuse region.

In another preferred embodiment, the conductive lines and via are formedof copper. Copper has better conductivity and can withstand highercurrent so that it is widely used for 0.13 μm and below. However, it ishard to etch. Therefore a damascene process is used. FIGS. 8 through 12are cross-sectional views of intermediate stages in the making of apreferred embodiment of the present invention using damascene process.FIG. 8 illustrates the formation of a lower-layer copper line 64. It isformed by forming a trench in the ILD 60, depositing a barrier layer 62in the trench, depositing copper, and performing a CMP to polish thecopper to the surface of the trench.

A dual damascene process is preferably performed to form a via and anupper-layer copper line. As shown in FIG. 9, a first etch stop layer 66,a first ILD 68, a second etch stop layer 70, a second ILD 72 and a hardmask 74 are formed. The materials and methods of forming these layersare known in the art. FIG. 10 illustrates a first opening 76 formed downto the first etch stop layer 66. A second opening 78 is formed in thesecond ILD 72. Then the exposed portion of the first etch stop layer 66is removed. The resulting structure is shown in FIG. 11. FIG. 12illustrates a structure with upper-layer copper line 82 and via 81. Abarrier layer 80 is conformally deposited in the openings 76 and 78.Copper is then deposited in the openings. A CMP is performed toplanarize the copper to the surface of upper-layer copper line 82.

Electrical fuses can be formed at different levels based on therequirements of the circuit design. FIG. 13 illustrates a stacked viastring coupled between conductive lines 100 and 111. Vias 102, 106 and109 are formed in different layers and are interconnected by conductiveislands 104 and 108. Islands 104 and 108 are coupled to external pads112 and 114, respectively. Therefore, the vias can be burned outindividually. The via string can also be used as one via. When a voltageis applied between pads 110 and 113, the weakest via is burned out firstand the whole via string is open. In a different embodiment of thepresent invention, the cross section of a via can take the shape ofsquare, rectangle, circle or other shapes. A via can also be tapered.

The e-fuse structure of the present invention can be non-borderless orborderless. FIG. 14 a illustrates a borderless structure. A via 124 ismisaligned with at least one of the conductive lines 120 and 126. Partof the via 124 extends out of the conductive lines 120 and 126. Theextension width E_(w) is preferably less than about ¾ of the via widthW. The misalignment typically does not affect the function of theelectrical fuse. It only lowers the current needed to burn the fuse. Ina non-borderless structure, the via 130 has no extension beyondconductive lines 128 and 132, as shown in FIG. 14 b.

FIGS. 15 a and 15 b illustrate applications of the preferred embodiment.FIG. 15 a illustrates an electrical circuit 148 coupled in series with afuse 146. The electrical circuit could be a circuit that may be replacedwhen it malfunctions. When the fuse 146 is burned out by applying acurrent through external pads 142 and 144, the electrical circuit 148 isdisconnected from the other circuits. FIG. 15 b illustrates an e-fuse134 coupled in parallel with a redundant circuit 136. One end of thee-fuse 134 is coupled to the ground. Therefore the redundant circuit 136is grounded by the e-fuse 134 and not activated. If a circuit element isfound defective and needs to be replaced by the redundant circuit 136, avoltage is applied to external pads 138 and 140 to burn the e-fuse 134.When the e-fuse 134 is open, the redundant circuit 136 is activated. Acircuit redundancy scheme can be established by combining the circuitsin FIG. 15 a and FIG. 15 b.

FIGS. 16 and 17 illustrate another embodiment of the present invention.FIG. 16 is a cross sectional view of the embodiment. A fuse comprising avia 168, a second-level conductive line 166, and a via group 170 isformed between two portions 160 ₁, 160 ₂ of a conductive line 160.Conductive line 160 and 166 are also referred to as conductive layers.Conductive line 160 ₁ is the cathode end and conductive line 160 ₂ isthe anode end. FIG. 17 is a top view of the embodiment. At the anodeend, via group 170 comprises two or more vias and can sustain highercurrent density than the via 168. With the asymmetric design, when thesame current flows through via 168 and via group 170, via 168 has highercurrent density than vias in the via group 170 and thus is more prone tobe burned out. Although FIG. 16 illustrates a preferred embodiment inwhich conductive line 166 is formed in a lower metal layer thanconductive lines 160 ₁ and 160 ₂, they may have different relativepositions in other embodiments. For example, assuming line 160 ₁ is inmetal layer m, the conductive line 166 may be in metal layer m−1, m+1,and metal lines 160 ₂ may be in other metal layers such as metal layerm−2, m+1, m+2, etc.

FIG. 18 illustrates a circuit for burning out a fuse. A fuse 176 isconnected in series with a transistor 178, which in this configurationis preferably an nMOS device. The fuse 176 and the transistor 178 arecoupled between power nodes Vcc and Vss, wherein the source of thetransistor 178 is connected to Vss, and the drain is connected to thefuse 176. When a high voltage is applied to the gate of the transistor178, transistor 178 conducts. A current flows through and burns fuse176. If the fuse to be burned has an asymmetric design as in FIGS. 16and 17, it is preferred that the cathode of the fuse, which is thesingle via end, is coupled to node 174, and the anode is coupled to thehigh power supply node Vcc. It is easier to burn the fuse with such aconnection. When a fuse illustrated in FIGS. 16 and 17 is used as thefuse 176, the cathode end 160 ₁ is preferably connected to the drain ofthe transistor 178, and the anode end 160 ₂ is preferably connected tothe power node Vcc.

The current density required for burning out a fuse is dependent on thematerial of the via and conductive lines, and the process used. Oneskilled in the art can find the right current density through routineexperiment. Table 1 presents exemplary data measured on the vias formedusing 90 nm technology. Dimension Burn-out Burn-out Current Layer (μm)Current (mA) density (A/cm²) M1 0.12 × 0.25 0.200 6.66 × 10⁵ M2˜M7 0.14× 0.325 0.312 6.86 × 10⁵ M8, M9 0.42 × 0.9 2.880 7.62 × 10⁵ Contact 0.12× 0.12 0.294 2.04 × 10⁶ Via 1˜Via 6 0.13 × 0.13 0.189 1.12 × 10⁶ Via 7,Via 8 0.36 × 0.36 1.452  8.8 × 10⁵ All stacked vias 0.13 × 0.13 0.1891.12 × 10⁶ except Via7 and 8 Stacked vias with Via 0.36 × 0.36 1.452 8.8 × 10⁵ 7 and Via 8

M1 through M9 are metal lines at different layers, with M9 being the toplayer metal, and M1 being the bottom layer metal. Via 1 is between M1and M2. Via2 is between M2 and M3, and via 8 is between M8 and M9.Typically, M8 and M9 are power lines so that they have the greatestthickness of 0.9 μm, which is the second value found in theirdimensions. The dimensions of M1 through M9 indicate width×thickness,and dimensions for vias indicate cross sectional dimensions.

In table 1, Rows marked as M1 through M9 present the current and currentdensity needed to burn out the metal lines. Rows marked as via1 throughvia8 present the current and current density needed to burn out thevias. The burn-out current density is calculated based on the burn-outcurrent divided by the cross sectional area, which in turn can becalculated from the dimension. While the current density to burn out thevia is affected by the material and process, the current for burning outa via is also affected by the cross sectional area. Preferably, thecross sectional area of the via is between about 1×10⁻⁴ μm² to about 1μm². By adjusting the cross sectional area for an e-fuse or a portion ofan e-fuse, the burn-out current can be adjusted into a desired range.One skilled in the art can take the factors such as the material,process, dimension, current, and current density into consideration sothat the structure comprising upper-layer conductive line, lower-layerconductive line and the via is adapted to be an e-fuse.

It is observed that in order to burn out the vias or the metal lines,the required current density is in the order of about 10⁵ A/cm² to about10⁶ A/cm². Although the data shows that the burn-out current density ofmetal lines are in the same order as, or some times even lower than theburn-out current density of vias, which suggests that the burn-outregion should occur in metal lines instead of vias, the experimentresults have revealed that the burn-out regions are typically in via orclose to the interfaces between the via and metals lines (refer to FIGS.16 a and 16 b), providing the burn-out current densities for metal linesare not too much lower than for vias. This result has indicated that thevias are suitable for e-fuses.

There is no special requirement as to the height of a via. The height ispreferably determined by the distance between metal layers. Thisprovides flexibility in the design of the fuse since the fuse design canbe easily integrated into the chip design without incurring extraprocessing steps and cost. In a preferred embodiment, the height isbetween about 500 Å to about 10000 Å.

FIGS. 19 a and 19 b illustrate side views of two examples of burnedfuses 154, which are coupled between two respective conductive lines 150and 152, of the present embodiment. Typically, the burned out region 156is close to the interfaces between the via and theupper-layer/lower-layer conductive lines. In FIG. 19 a, the burn outregion 156 is mainly in via 154. In FIG. 19 b, the burn out region 156extends to one of the conductive lines 152.

There are several advantages features provided by the embodiments of thepresent invention. These include (but are not limited to): first, higherrepairable rate can be achieved since the burn out process is easier tocontrol and more reliable. Second, fewer masking layers is requiredtherefore reducing cost. Third, the preferred embodiments provide aflexible structure for circuit designers. The fuse may reside in anyregion of the inter layer vias for cell size reduction.

Although the present invention and its advantages have been described indetail, it should be understood that various changes, substitutions andalterations can be made herein without departing from the spirit andscope of the invention as defined by the appended claims. Moreover, thescope of the present application is not intended to be limited to theparticular embodiments of the process, machine, manufacture, andcomposition of matter, means, methods and steps described in thespecification. As one of ordinary skill in the art will readilyappreciate from the disclosure of the present invention, processes,machines, manufacture, compositions of matter, means, methods, or steps,presently existing or later to be developed, that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein may be utilized according tothe present invention. Accordingly, the appended claims are intended toinclude within their scope such processes, machines, manufacture,compositions of matter, means, methods, or steps.

1. An electrical fuse comprising: a first conductive layer; a secondconductive layer; and a via coupled between the first conductive layerand the second conductive layer wherein at least one of the via, thefirst conductive layer and the second conductive layer are adapted to bean electrical fuse.
 2. The electrical fuse of claim 1 wherein theelectrical fuse further comprises a first external pad coupled to thefirst conductive layer; and a second external pad coupled to the secondconductive layer.
 3. The electrical fuse of claim 1 further comprising:a third conductive layer; and a plurality of vias coupled between thesecond conductive layer and the third conductive layer.
 4. Theelectrical fuse of claim 3 further comprising: an nMOS transistor havinga drain coupled to the third conductive layer; and a source coupled to afirst power supply node wherein the first conductive layer is coupled toa second power supply node.
 5. The electrical fuse of claim 1 whereinthe via has a cross sectional area of between about 10⁻⁴ μm² and about 1μm².
 6. The electrical fuse of claim 1 wherein the via has a height ofbetween about 500 Å and about 1 μm.
 7. The electrical fuse of claim 1wherein the via comprises a conductive material and a barrier layeroutside the conductive material.
 8. The electrical fuse of claim 1further comprising: a plurality of additional vias each in a differentlayer; and a plurality of additional conductive layers wherein theadditional vias are coupled in series and each of the additional vias iscoupled between two of the additional conductive layers.
 9. Theelectrical fuse of claim 8 further comprising: a plurality of externalpads each coupled to one of the additional conductive layers.
 10. Theelectrical fuse of claim 1 wherein the first conductive layer, thesecond conductive layer and the via comprise copper and are formed by amethod selected from the group consisting of single damascene processand dual damascene process.
 11. The electrical fuse of claim 1 whereinthe via is misaligned to the first and/or the second conductive layers.12. The electrical fuse of claim 12 wherein the misalignment is smallerthan about ¾ of the via dimension in the misalignment direction.
 13. Asemiconductor device comprising: a burned-out electrical fusecomprising: a first conductive layer; a second conductive layer; and avia coupled between the first conductive layer and the second conductivelayer and adapted to be a fuse.
 14. The electrical fuse of claim 13wherein the electrical fuse comprises a first external pad coupled tothe first conductive layer; a second external pad coupled to the secondconductive layer; and an electrical discontinuity in the via or adjacentthe interfaces between the via and the first and the second conductivelayers.
 15. The electrical fuse of claim 14 further comprising aplurality of vias between the first and the second external pads. 16.The electrical fuse of claim 13 further comprising: a third conductivelayer; and a plurality of vias coupled between the second conductivelayer and the third conductive layer wherein the vias are notburned-out.
 17. The electrical fuse of claim 13 wherein the via has across sectional area of between about 10⁻⁴ μm² and about 1 μm².
 18. Asemiconductor device comprising: an electrical circuit; a redundantcircuit having a redundant design of the electrical circuit; a firstconductive layer; a second conductive layer; and a first via coupledbetween the first conductive layer and the second conductive layerwherein one of the first and second conductive layers is coupled to theredundant circuit and wherein the first via, the first conductive layerand the second conductive layer are adapted to be an electrical fuse.19. The semiconductor device of claim 18 further comprises a firstexternal pad coupled to the first conductive layer; and a secondexternal pad coupled to the second conductive layer.
 20. Thesemiconductor device of claim 18 further comprising: a second viacoupled in parallel with the electrical circuit; wherein the second viais coupled between a third conductive layer and a fourth conductivelayer; wherein the second via, the third conductive layer and the fourthconductive layer are adapted to be an electrical fuse; a third externalpad coupled to the third conductive layer; and a fourth external padcoupled to the fourth conductive layer.